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<span style="color:#898887;">--------------------------------------------------------------------------------</span>
<span style="color:#898887;">-- light52_tb.vhdl -- </span>
<span style="color:#898887;">--------------------------------------------------------------------------------</span>
<span style="color:#898887;">-- This test bench simulates the execution of some program (whose object code</span>
<span style="color:#898887;">-- is in package obj_code_pkg, in the form of a memory init constant) and logs</span>
<span style="color:#898887;">-- the execution to a text file called 'hw_sim_log.txt' (light52_tb_pkg.vhdl).</span>
<span style="color:#898887;">--</span>
<span style="color:#898887;">-- This test bench does no actual tests on the core. Instead, the simulation log</span>
<span style="color:#898887;">-- is meant to be matched against the simulation log produced by running the </span>
<span style="color:#898887;">-- same program on the software simulator B51 (also included with this project).</span>
<span style="color:#898887;">-- </span>
<span style="color:#898887;">-- This will catch errors in the implementation of the CPU if the simulated</span>
<span style="color:#898887;">-- program has anough coverage -- the opcode tester is meant to cover all CPU</span>
<span style="color:#898887;">-- opcodes in many (not all) of their corner cases.</span>
<span style="color:#898887;">-- This scheme will not help in catching errors in the peripheral modules, </span>
<span style="color:#898887;">-- mainly because the current version of B51 does not simulate them.</span>
<span style="color:#898887;">--</span>
<span style="color:#898887;">--------------------------------------------------------------------------------</span>
<span style="color:#898887;">-- Copyright (C) 2012 Jose A. Ruiz</span>
<span style="color:#898887;">--                                                              </span>
<span style="color:#898887;">-- This source file may be used and distributed without         </span>
<span style="color:#898887;">-- restriction provided that this copyright statement is not    </span>
<span style="color:#898887;">-- removed from the file and that any derivative work contains  </span>
<span style="color:#898887;">-- the original copyright notice and the associated disclaimer. </span>
<span style="color:#898887;">--                                                              </span>
<span style="color:#898887;">-- This source file is free software; you can redistribute it   </span>
<span style="color:#898887;">-- and/or modify it under the terms of the GNU Lesser General   </span>
<span style="color:#898887;">-- Public License as published by the Free Software Foundation; </span>
<span style="color:#898887;">-- either version 2.1 of the License, or (at your option) any   </span>
<span style="color:#898887;">-- later version.                                               </span>
<span style="color:#898887;">--                                                              </span>
<span style="color:#898887;">-- This source is distributed in the hope that it will be       </span>
<span style="color:#898887;">-- useful, but WITHOUT ANY WARRANTY; without even the implied   </span>
<span style="color:#898887;">-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      </span>
<span style="color:#898887;">-- PURPOSE.  See the GNU Lesser General Public License for more </span>
<span style="color:#898887;">-- details.                                                     </span>
<span style="color:#898887;">--                                                              </span>
<span style="color:#898887;">-- You should have received a copy of the GNU Lesser General    </span>
<span style="color:#898887;">-- Public License along with this source; if not, download it   </span>
<span style="color:#898887;">-- from http://www.opencores.org/lgpl.shtml</span>
<span style="color:#898887;">--------------------------------------------------------------------------------</span>


<span style="font-weight:bold;">library</span> ieee;
<span style="font-weight:bold;">use</span> ieee<span style="color:#006e28;">.</span>std_logic_1164<span style="color:#006e28;">.</span>all;
<span style="font-weight:bold;">use</span> ieee<span style="color:#006e28;">.</span>std_logic_arith<span style="color:#006e28;">.</span>all;
<span style="font-weight:bold;">use</span> ieee<span style="color:#006e28;">.</span>std_logic_unsigned<span style="color:#006e28;">.</span>all;
<span style="font-weight:bold;">use</span> std<span style="color:#006e28;">.</span>textio<span style="color:#006e28;">.</span>all;

<span style="font-weight:bold;">use</span> work<span style="color:#006e28;">.</span>light52_pkg<span style="color:#006e28;">.</span>all;
<span style="font-weight:bold;">use</span> work<span style="color:#006e28;">.</span>obj_code_pkg<span style="color:#006e28;">.</span>all;
<span style="font-weight:bold;">use</span> work<span style="color:#006e28;">.</span>light52_tb_pkg<span style="color:#006e28;">.</span>all;
<span style="font-weight:bold;">use</span> work<span style="color:#006e28;">.</span>txt_util<span style="color:#006e28;">.</span>all;

<span style="color:#223388;font-weight:bold;">entity</span> <span style="color:#bb6600;font-weight:bold;">light52_tb</span> <span style="font-weight:bold;">is</span>
<span style="color:#223388;font-weight:bold;">generic</span> (BCD <span style="color:#006e28;">:</span> <span style="color:#0057ae;">boolean</span> <span style="color:#006e28;">:=</span> true);
<span style="color:#223388;font-weight:bold;">end;</span>


<span style="color:#223388;font-weight:bold;">architecture</span> <span style="color:#bb6600;font-weight:bold;">testbench</span> <span style="font-weight:bold;">of</span> <span style="color:#644a9b;">light52_tb</span> <span style="font-weight:bold;">is</span>

<span style="color:#898887;">--------------------------------------------------------------------------------</span>
<span style="color:#898887;">-- Simulation parameters</span>
<span style="color:#898887;">-- FIXME these should be in parameter package</span>

<span style="color:#898887;">-- Simulated clock period is the same as the usual target, the DE-1 board</span>
<span style="color:#006e28;">constant</span> T <span style="color:#006e28;">:</span> <span style="color:#0057ae;">time</span> <span style="color:#006e28;">:=</span> <span style="color:#b08000;">20</span> <span style="color:#0057ae;">ns</span>; <span style="color:#898887;">-- 50MHz</span>
<span style="color:#006e28;">constant</span> SIMULATION_LENGTH <span style="color:#006e28;">:</span> <span style="color:#0057ae;">integer</span> <span style="color:#006e28;">:=</span> <span style="color:#b08000;">400000</span>;

<span style="color:#898887;">--------------------------------------------------------------------------------</span>
<span style="color:#898887;">-- MPU interface </span>

<span style="color:#006e28;">signal</span> clk <span style="color:#006e28;">:</span>                <span style="color:#0057ae;">std_logic</span> <span style="color:#006e28;">:=</span> <span style="color:#b08000;">'0'</span>;
<span style="color:#006e28;">signal</span> reset <span style="color:#006e28;">:</span>              <span style="color:#0057ae;">std_logic</span> <span style="color:#006e28;">:=</span> <span style="color:#b08000;">'1'</span>;

<span style="color:#006e28;">signal</span> p0_out <span style="color:#006e28;">:</span>             <span style="color:#0057ae;">std_logic_vector</span>(<span style="color:#b08000;">7</span> <span style="color:#006e28;">downto</span> <span style="color:#b08000;">0</span>);
<span style="color:#006e28;">signal</span> p1_out <span style="color:#006e28;">:</span>             <span style="color:#0057ae;">std_logic_vector</span>(<span style="color:#b08000;">7</span> <span style="color:#006e28;">downto</span> <span style="color:#b08000;">0</span>);
<span style="color:#006e28;">signal</span> p2_in <span style="color:#006e28;">:</span>              <span style="color:#0057ae;">std_logic_vector</span>(<span style="color:#b08000;">7</span> <span style="color:#006e28;">downto</span> <span style="color:#b08000;">0</span>);
<span style="color:#006e28;">signal</span> p3_in <span style="color:#006e28;">:</span>              <span style="color:#0057ae;">std_logic_vector</span>(<span style="color:#b08000;">7</span> <span style="color:#006e28;">downto</span> <span style="color:#b08000;">0</span>);

<span style="color:#006e28;">signal</span> external_irq <span style="color:#006e28;">:</span>       <span style="color:#0057ae;">std_logic_vector</span>(<span style="color:#b08000;">7</span> <span style="color:#006e28;">downto</span> <span style="color:#b08000;">0</span>);

<span style="color:#006e28;">signal</span> txd<span style="color:#006e28;">,</span> rxd <span style="color:#006e28;">:</span>           <span style="color:#0057ae;">std_logic</span>;

<span style="color:#898887;">--------------------------------------------------------------------------------</span>
<span style="color:#898887;">-- Logging signals &amp; simulation control </span>

<span style="color:#898887;">-- Asserted high to disable the clock and terminate the simulation.</span>
<span style="color:#006e28;">signal</span> done <span style="color:#006e28;">:</span>               <span style="color:#0057ae;">std_logic</span> <span style="color:#006e28;">:=</span> <span style="color:#b08000;">'0'</span>;

<span style="color:#898887;">-- Log file</span>
<span style="font-weight:bold;">file</span> log_file<span style="color:#006e28;">:</span> <span style="color:#0057ae;">TEXT</span> <span style="font-weight:bold;">open</span> write_mode <span style="font-weight:bold;">is</span> <span style="color:#bf0303;">&quot;hw_sim_log.txt&quot;</span>;
<span style="color:#898887;">-- Console output log file</span>
<span style="font-weight:bold;">file</span> con_file<span style="color:#006e28;">:</span> <span style="color:#0057ae;">TEXT</span> <span style="font-weight:bold;">open</span> write_mode <span style="font-weight:bold;">is</span> <span style="color:#bf0303;">&quot;hw_sim_console_log.txt&quot;</span>;
<span style="color:#898887;">-- Info record needed by the logging fuctions</span>
<span style="color:#006e28;">signal</span> log_info <span style="color:#006e28;">:</span>           t_log_info;

<span style="color:#223388;font-weight:bold;">begin</span>

<span style="color:#898887;">---- UUT instantiation ---------------------------------------------------------</span>

<span style="color:#bb6600;font-weight:bold;">uut</span><span style="color:#006e28;">:</span> <span style="color:#644a9b;">entity work.light52_mcu</span>
    <span style="font-weight:bold;">generic map (</span>
        IMPLEMENT_BCD_INSTRUCTIONS <span style="color:#006e28;">=&gt;</span> BCD<span style="color:#006e28;">,</span>
        CODE_ROM_SIZE <span style="color:#006e28;">=&gt;</span>    work<span style="color:#006e28;">.</span>obj_code_pkg<span style="color:#006e28;">.</span>XCODE_SIZE<span style="color:#006e28;">,</span>
        XDATA_RAM_SIZE <span style="color:#006e28;">=&gt;</span>   work<span style="color:#006e28;">.</span>obj_code_pkg<span style="color:#006e28;">.</span>XDATA_SIZE<span style="color:#006e28;">,</span>
        OBJ_CODE <span style="color:#006e28;">=&gt;</span>         work<span style="color:#006e28;">.</span>obj_code_pkg<span style="color:#006e28;">.</span>object_code
    )
    <span style="font-weight:bold;">port map (</span>
        clk             <span style="color:#006e28;">=&gt;</span> clk<span style="color:#006e28;">,</span>
        reset           <span style="color:#006e28;">=&gt;</span> reset<span style="color:#006e28;">,</span>
        
        txd             <span style="color:#006e28;">=&gt;</span> txd<span style="color:#006e28;">,</span>
        rxd             <span style="color:#006e28;">=&gt;</span> rxd<span style="color:#006e28;">,</span>
        
        external_irq    <span style="color:#006e28;">=&gt;</span> external_irq<span style="color:#006e28;">,</span>
                
        p0_out          <span style="color:#006e28;">=&gt;</span> p0_out<span style="color:#006e28;">,</span>
        p1_out          <span style="color:#006e28;">=&gt;</span> p1_out<span style="color:#006e28;">,</span>
        p2_in           <span style="color:#006e28;">=&gt;</span> p2_in<span style="color:#006e28;">,</span>
        p3_in           <span style="color:#006e28;">=&gt;</span> p3_in
    );
    
    <span style="color:#898887;">-- UART is looped back in the test bench.</span>
    rxd <span style="color:#006e28;">&lt;=</span> txd;
    
    <span style="color:#898887;">-- I/O ports are looped back and otherwise unused.</span>
    p2_in <span style="color:#006e28;">&lt;=</span> p0_out;
    p3_in <span style="color:#006e28;">&lt;=</span> p1_out;
    
    <span style="color:#898887;">-- External IRQ inputs are tied to port P1 for test purposes</span>
    external_irq <span style="color:#006e28;">&lt;=</span> p1_out;

    <span style="color:#898887;">---- Master clock: free running clock used as main module clock ------------</span>
    <span style="color:#bb6600;font-weight:bold;">run_master_clock</span><span style="color:#006e28;">:</span> <span style="color:#0099aa;font-weight:bold;">process</span>(done<span style="color:#006e28;">,</span> clk)
    <span style="color:#0099aa;font-weight:bold;">begin</span>
        <span style="color:#223388;font-weight:bold;">if</span> done <span style="color:#006e28;">=</span> <span style="color:#b08000;">'0'</span> <span style="color:#223388;font-weight:bold;">then</span>
            clk <span style="color:#006e28;">&lt;=</span> <span style="font-weight:bold;">not</span> clk <span style="font-weight:bold;">after</span> T<span style="color:#006e28;">/</span><span style="color:#b08000;">2</span>;
        <span style="color:#223388;font-weight:bold;">end if;</span>
    <span style="color:#0099aa;font-weight:bold;">end process run_master_clock</span>;


    <span style="color:#898887;">---- Main simulation process: reset MCU and wait for fixed period ----------</span>

    <span style="color:#bb6600;font-weight:bold;">drive_uut</span><span style="color:#006e28;">:</span> <span style="color:#0099aa;font-weight:bold;">process</span>
    <span style="color:#0099aa;font-weight:bold;">begin</span>
        <span style="color:#898887;">-- Leave reset asserted for a few clock cycles...</span>
        reset <span style="color:#006e28;">&lt;=</span> <span style="color:#b08000;">'1'</span>;
        <span style="font-weight:bold;">wait</span> <span style="font-weight:bold;">for</span> T<span style="color:#006e28;">*</span><span style="color:#b08000;">4</span>;
        reset <span style="color:#006e28;">&lt;=</span> <span style="color:#b08000;">'0'</span>;
        
        <span style="color:#898887;">-- ...and wait for the test to hit a termination condition (evaluated by</span>
        <span style="color:#898887;">-- function log_cpu_activity) or to just timeout.</span>
        <span style="font-weight:bold;">wait</span> <span style="font-weight:bold;">for</span> T<span style="color:#006e28;">*</span>SIMULATION_LENGTH;

        <span style="color:#898887;">-- If we arrive here, the simulation timed out (termination conditions</span>
        <span style="color:#898887;">-- trigger a failed assertion).</span>
        <span style="color:#898887;">-- So print a timeout message and quit.</span>
        print(<span style="color:#bf0303;">&quot;TB timed out.&quot;</span>);
        done <span style="color:#006e28;">&lt;=</span> <span style="color:#b08000;">'1'</span>;
        <span style="font-weight:bold;">wait</span>;
        
    <span style="color:#0099aa;font-weight:bold;">end process drive_uut</span>;


    <span style="color:#898887;">-- Logging process: launch logger functions --------------------------------</span>
    <span style="color:#bb6600;font-weight:bold;">log_execution</span><span style="color:#006e28;">:</span> <span style="color:#0099aa;font-weight:bold;">process</span>
    <span style="color:#0099aa;font-weight:bold;">begin</span>
        <span style="color:#898887;">-- Log cpu activity until done='1'.</span>
        log_cpu_activity(clk<span style="color:#006e28;">,</span> reset<span style="color:#006e28;">,</span> done<span style="color:#006e28;">,</span> <span style="color:#bf0303;">&quot;/uut&quot;</span><span style="color:#006e28;">,</span>
                         log_info<span style="color:#006e28;">,</span> work<span style="color:#006e28;">.</span>obj_code_pkg<span style="color:#006e28;">.</span>XCODE_SIZE<span style="color:#006e28;">,</span> <span style="color:#bf0303;">&quot;log_info&quot;</span><span style="color:#006e28;">,</span> 
                         X<span style="color:#bf0303;">&quot;0000&quot;</span><span style="color:#006e28;">,</span> log_file<span style="color:#006e28;">,</span> con_file);
        
        <span style="color:#898887;">-- Flush console log file when finished.</span>
        log_flush_console(log_info<span style="color:#006e28;">,</span> con_file);
        
        <span style="font-weight:bold;">wait</span>;
    <span style="color:#0099aa;font-weight:bold;">end process log_execution</span>;

<span style="color:#223388;font-weight:bold;">end architecture testbench;</span>


<span style="color:#898887;">-- these should be the same, see bug #368897</span>
A(A<span style="color:#b08000;">'high</span>)  <span style="color:#898887;">-- comment</span>
A(A<span style="color:#b08000;">'high</span> ) <span style="color:#898887;">-- comment</span>

</pre></body></html>
